My prior patents describe a number of embodiments of novel magneto-electronic elements which have beneficial uses in a wide variety of environments.
For example, the physical theory, structure and operation of a novel magnetic (or metal) spin transistor (MST) device used as a read head for a magnetic hard disk is described in U.S. Pat. No. 5,432,373. Further, in my U.S. Pat. No. 5,565,695 I described, among other things, the specific structure and operation of an improved MST device with broader applicability to a wider variety of environments, including non-volatile storage. A typical application for such MST device includes use as memory cell in an array of independent, randomly accessible elements, as a replacement for traditional magnetic storage media, DRAM, etc. As also indicated in the '695 patent, a typical semiconductor element such as a FET (or diode) can be used to great advantage to isolate and couple magnetic spin transistor elements in such arrays.
Similarly, in U.S. Pat. No. 5,629,549, the same novel magnetic spin transistor devices are described as building blocks of novel and powerful logic gates. Through suitable selections of input signals and/or configuration states of the ferromagnetic layers of such devices, a variety of conventional Boolean logic operations can be effectuated, including AND, OR, NAND, NOR, NOT, etc. The aforementioned patent also explains a further useful implementation in which the output of one device is inductively coupled to drive an input of a next stage device.
Additionally, in U.S. Pat. No. 5,654,566, yet another useful embodiment of a magnetic spin transistor is described, in which base and (configurable) collector ferromagnetic layers are coupled directly to the source and drain of a conventional semiconductor field effect transistor. In this manner, the conductivity of a FET channel can be controlled to permit or inhibit flow of spin polarized electrons between the two ferromagnetic layers. Depending on the orientation of the collector layer vis-a-vis the base, the amount of spin current will vary, thus implementing a non-volatile memory or logic element that is integrated with conventional silicon gate technology.
Finally, in U.S. Pat. No. 5,652,445 I introduced yet another magneto-electronic element which is referred to generally as a Hybrid Hall Effect (HHE) device. Unlike the MST devices above, the HHE device does not make use of spin-polarized current, but, rather, a conventional electron current induced in a Hall plate by a configurable ferromagnetic layer coupled to the Hall plate. Nevertheless, the HHE device inherently includes all of the operational benefits of the MST devices above, including non-volatility, flexible and useful configurability of the magnetization states, small feature size, ease of manufacturability, etc.
Furthermore, unlike any conventional semiconductor devices known to the applicant, both the HHE and MST devices above have operational characteristics that scale inversely with size. In other words, for a constant current source, the readout voltage is improved as device size is decreased. This feature alone makes such devices an especially attractive alternative to typical semiconductor devices for extremely small geometries.
Consequently, the physics, structure, operation and formation of magnetic spin transistor and HHE devices are well known based on the description in my prior patents, including U.S. Pat. Nos. 5,432,373, 5,629,549, 5,565,695, 5,654,566 and 5,652,445.
As a general rule in the art of electronics, with all things being equal, a most useful circuit is one that uses the least number of devices (highest integration) to perform the most functions. For this reason, skilled artisans spend considerable man-hours each year trying to come up with designs for conventional logic circuits (such as boolean function units, boolean logic gates, adders, multipliers, etc.) that require the least number of active devices to implement. This dynamic is based on the fact that again, all things being equal, fewer devices generally translate into higher processing density, lower power, higher speed, lower cost, etc. To date, such circuits have been implemented in a variety of silicon based technologies (RTL, TTL, CMOS, ECL, BiCMOS, etc.) and while improvements have been made in each such family, it is apparent that there is significant need for alternative technologies that minimize the number of electronic elements required to implement many commonly used functional logic circuits.
An example of a typical prior art universal logic circuit is depicted in U.S. Pat. No. 4,558,236 (Barrows). This reference shows a circuit that performs any one of a number of logic functions on two input signals; the particular logic function is dictated by a control signal. The circuit in Barrows, nevertheless, consists of at least 8 separate FETs not counting additional logic required to generate the inverse of at least one of the input signals.
A reference by Weste & Eshragian entitled "Principles of CMOS VLSI Design" (Addison-Wesley Publishing Co., 2.sup.nd edition, 1993, pp. 306-307) also shows a typical multi-functional logic circuit known generally as a "Boolean Function Unit." This circuit, depicted in FIG. 5.35 of that reference, generates any one of 5 logical functions based on two inputs A and B, including AND, OR, NOR, NAND and XOR. The particular function implemented by the circuit is controlled by control signals P1, P2, P3 and P4 in the manner shown in Table 5.9 therein. As can be seen in this figure, however, the number of elements required to effectuate these five functions is at least eight separate FETs for NMOS implementation and 16 separate FETs for a CMOS implementation.
Similarly, a prior art 4*4 bit multiplier as described by Weste et. al. at pp. 545-547 is shown in FIG. 8.36. This type of circuit implemented with purely conventional semiconductor technology requires some 624 separate FETs, which take up an extremely large amount of substrate area. Weste also illustrates a traditional single bit adder at p.517, which can be seen as calling for some 28 transistors. Finally, a typical shifter circuit is also shown on pp. 560-562, and this corresponds generally to the circuit shown in FIG. 8.46 which includes some 56 separate FETs.
A common feature of all of these circuits is that they are extremely vital and necessary to the operation of many conventional processing units used today, but they nevertheless are commercially difficult to implement in a cost effective manner because they require so many active elements and so much associated chip space. While my prior patents have already discussed various magneto-electronic devices well suited for replacing single logic gates, to date there has been no attempt made to utilize such devices in higher level logic circuits such as the above.
In addition, there has also been a continuous need in the electronics industry for a single logic device that can be configured and reconfigured dynamically to perform more than one logical function at a time. While there are some dynamically reconfigurable systems (i.e., large collections of gates corresponding to larger sets of active devices) in the prior art, to date there has been no instance of such functionality existing to implement a reconfigurable logical function for a single gate, or at an even more granular level, a single reconfigurable device. As an example, certain prior art programmable logic devices by companies such as Atmel and Lattice have some portions that are re-configurable. However, the functionality of these systems is only controllable at a relatively high level and the speed of re-programmability is relatively slow. There is no mechanism in such devices for transforming a single OR logic function block into an AND function block, and more fundamentally, for altering the FETs in an OR circuit to instead implement an AND function. In this respect, FIG. 1 is instructive, in that it depicts a typical prior art circuit implementing a NAND function for two single data inputs A and B. As can be seen here, even though this is a simple logic function, it nevertheless requires four (4) active FET devices, as well as associated interconnects and necessary isolation regions. Once such a device is fabricated in silicon, there is no means for "transforming" it into a different type of logic gate, and certainly no mechanism known for controlling a single FET to alter its behavior for example to switch from a p type to an n type device. Consequently it is apparent that a flexible, transformable logic device of this type would be an attractive replacement for conventional FETs.
Of equal importance and concern in the prior art is the relative integration density required to implement a particular set of logic functions. For example, Programmable Logic Devices (PLDs) are generally comprised of a large number of identical "macrocells" that are interconnected in some fashion to effectuate a desired result on a particular set of inputs and intermediary data/logic values. All things being equal, it is clearly most desirable to maximize the functionality (i.e., number of possible logical functions) of such macrocells while simultaneously minimizing the size of such a structure. There are limits to what can be done to effectuate these critical design parameters, however, given the peculiarities and requirements of conventional semiconductor devices.
Moreover, while it would be indisputably useful in many instances, there are no simple PLDs or macrocells (to applicant's knowledge) that have the capability of generating multiple, time sequenced logic functions on a set of input signals. In other words, a single, simple circuit that generates multiple different boolean logic outputs at different clock cycles could have enormous utility in some applications.
Furthermore, to date no logic device known to applicant performs two different logical functions based solely on the characteristics of the input signals. For example, in some environments it may be useful to have a logic circuit behave in two different ways in response to two sets of logically similar but physically different signals. In other words, a logical "one" can be generated physically by circuit X in the form of a signal having an amplitude I, and by another circuit Y in the form of a signal having an amplitude I/2. If both circuits can transmit their respective outputs to a common, succeeding stage, and if this stage can operate to effectuate two different logical functions (i.e., behave as an AND circuit for the outputs of X, and as an OR circuit for the outputs of Y) then this would further increase the density of an integrated circuit.